The present invention relates to the field of phase-locked loops.
Unlike a phase-locked loop (PLL) with a self-oscillating oscillator, a phase-locked loop with a delay element (i.e., a delay locked loop—DLL) has the problem that the delayed output signals of the delay element are indistinguishable for all delays that correspond to an integer multiple of the clock pulse of the input signal. Therefore, the danger exists that the delay time will be set as an indeterminate integer multiple of the period of the input signal.
To prevent this from occurring, one known method is to limit the possible delay time of the delay element. However, this measure has the disadvantage that the frequency range is significantly limited. Especially in the case of integrated circuits, there is the additional problem that absolute precision is required for the limiter. If the ratio of the signal to the clock pulse space of the input signal deviates from 50%, an additional downward limitation of the delay time is required, with the result that the frequency range is limited still further.
Another known approach avoids the setting of the delay time as an indeterminate integer multiple of the period of the input signal by generating an allocation or detection of the association of the edges of the output signal with the edges of the input signal. However, this approach is quite complex and expensive, and almost impossible to implement, especially at high frequencies.
Therefore, there is a need for a phase-locked loop in which nonpermissible delay times are detected and eliminated by appropriate corrections.